The present invention relates to programmable memories, to programmable read-only memories (PROMs) and, in particular, to a fuse programmable ROM which uses oxide breakdown between narrow selectively formed sidewall conductor structures and diffusion regions. The invention also relates to a method for making a fuse programmable ROM in which a tungsten fuse is deposited as part of a contemporary tungsten-polysilicon shunt deposition procedure during otherwise conventional fabrication of field effect type integrated circuits.
Programmable ROMs are known in which the cells of a ROM memory array contain fusible links. Various fusible link ROM designs are available in which the manufacturer or customer applies high currents to selected bit locations to blow the fusible links so that the associated transistor is open and does not conduct current. The ROM is thus permanently programmed to a selected 1/0 pattern of conducting and non-conducting bits.
Conversely, the fusible link technology has also been used to break down an insulator to thus complete a conduction path for active and passive devices. For example, U.S. Pat. No. 3,576,549, issued Apr. 27, 1971, to Hess, forms a contact on an insulating layer over a semiconductor substrate. The substrate contains a device such as a diode or bipolar transistor. The device is programmed by applying to the conductor a voltage of sufficient magnitude and duration to break down the insulator between the contact and the device so that the conductor makes ohmic contact with the device. U.S. Pat. No. 3,787,822, issued Jan. 22, 1974, to Rioult, discloses a programmable read-only memory which uses a somewhat similar approach. Basically, the approach involves completing a conduction path from a contact to an underlying metallic conductor which itself contacts the emitter of a bipolar transistor formed in a semiconductor substrate. Like the Hess patent, Rioult establishes ohmic contact by applying a voltage to break down an oxide layer which, in this case, is interposed between the contact and the metal conductor.
Another vertical fuse technique is described in U.S. Pat. No. 4,312,046, issued Jan. 19, 1982, to Taylor. Here, programmable read-only memories are provided by an array of bipolar devices formed in a substrate having surface-adjacent emitters beneath an aluminum conductor. The device emitters each form a programmable Schottky diode with the aluminum contact material. The diode is vertically shorted by applying a voltage across the diode to cause vertical electromigration of aluminum atoms to short the conductor directly to the emitter.
More recent approaches to breaking down or otherwise degrading dielectric layers to selectively form conductive paths in the course of programming are disclosed in U.S. Pat. No. 4,543,594 granted to inventors Mohsen et al. and U.S. Pat. Nos. 4,507,756 and 4,507,757 to inventor McElroy. The first of the noted patents relates to use of direct silicon dioxide breakdown, while the latter two extend the breakdown concepts by utilizing excentuated fringing fields to degrade a silicon dioxide layer in the course of forming conductive paths therethrough. These techniques unfortunately require special breakdown dielectric fabrication sequences, distinct from the steps commonly employed to fabricate field effect transistors, and, by virtue of the relatively large area subject to alteration during programming, require the inclusion of programming current limiting circuitry.
In view of the unique fabrication requirements imposed by the prior art approaches, it is one object of the present invention to provide a simple vertical fuse technique for programmable read-only memories which is implemented by, and is formed without departing from, the contemporary circuit fabrication process.
It is also an object of this invention to provide such a vertical fuse PROM technique which is applicable to low current integrated circuit technologies, featuring a structurally created programming current limitation.
It is also an object to integrate the vertical fuse element with a polysilicon conductor-to-diffusion structure by using a basic integrated circuit processing, using only a single additional masking step.